Silicon wafers used in electronic devices are typically prepared from a single crystal silicon ingot that is first sliced into thin wafers using a diamond saw, lapped to improve flatness, and etched to remove subsurface damage caused by lapping. The silicon wafers are then typically polished in a two-step process to remove nanotopography caused by etching and to achieve the desired thickness before the wafers are acceptable for use in electronic devices.
In the first polishing step, a high removal rate is required, and ideally the nanotopography is not degraded during this step. Nanotopography is a parameter that measures the front-surface topology of an area and is defined as the deviation of a surface within a spatial wavelength of about 0.2 mm to 20 mm. Nanotopography differs from surface flatness in that, for nanotopography, the flatness of the wafer surface is measured relative to the wafer surface itself, while for surface flatness, the flatness of the wafer surface is measured relative to a flat chuck used to hold the wafer. Thus, a wafer may have perfect flatness, yet still have nanotopography. If a wafer has surface irregularities on the front and back sides of the wafer, but the front and back surfaces are parallel, the wafer has perfect flatness. However, the same wafer will exhibit nanotopography. Nanotopography bridges the gap between roughness and flatness in the topology map of wafer surface irregularities in spatial frequency.
The roughness of a surface can be specified using several parameters, which consider roughness in terms of deviations from the horizontal plane of the mean surface level. For example, one parameter for measuring roughness is RMS roughness, which is the root mean squared value of all vertical deviations from the mean surface level. Another parameter for measuring roughness is surface roughness or average roughness (Ra), which is the arithmetical mean of deviations from planarity from the mean surface level. The distribution of roughness versus spatial frequency of features is defined by the Power Spectral Density (PSD) function or Power Spectrum. The PSD provides surface roughness data by computing the spatial power spectrum from an image of the surface.
The polishing process for silicon wafers results in a degree of roughness, even if only at the atomic level. Correct function of the fabricated component often is critically dependent on its degree of roughness. For example, computer hard disks have a narrow tolerance band for acceptable roughness. If the surface is too smooth, the read/write head may bind to the surface of the disk. If the surface is too rough, the head may be unable to fly over the disk surface on its air cushion in the proper manner. Moreover, surface roughness can affect a component's chemical and physical stability. Surfaces that have to stand up to hostile environments (e.g., temperature, humidity, or chemicals) must be as smooth as possible in order to present the minimum surface area for attack, and to have as few defects or weak spots as possible.
Conventional polishing compositions for silicon wafers exhibit high removal rates for silicon, but produce increased nanotopography and roughness of the silicon wafers. The increased nanotopography puts increased demands on the second, final polishing step to produce silicon wafers suitable for further processing into semiconductor substrates.
Thus, there remains an important need in the art for improved polishing compositions for silicon wafers.